We have a custom board using a T4240 Rev 2. Our DDR uses a 100Mhz input clock and can only operate up to 1200 (600 DDR CLK). We are using "CW JTAG Config" to connect to the board before a RCW has been programmed into flash. We noticed however that it does not matter what we set MEM_PLL_RATIO the forced clock is always set to 2400 (1200 DDR CLK).
Are we doing something wrong or is the MEM_PLL_RATIO fixed when forcing a RCW using CW JTAG?