T4240 CW JTAG CONFIG does not set DDR clock

cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 

T4240 CW JTAG CONFIG does not set DDR clock

464 Views
reedy
Contributor III

We have a custom board using a T4240 Rev 2. Our DDR uses a 100Mhz input clock and can only operate up to 1200 (600 DDR CLK). We are using "CW JTAG Config" to connect to the board before a RCW has been programmed into flash. We noticed however that it does not matter what we set MEM_PLL_RATIO the forced clock is always set to 2400 (1200 DDR CLK).


Are we doing something wrong or is the MEM_PLL_RATIO fixed when forcing a RCW using CW JTAG?   

0 Kudos
2 Replies

318 Views
addiyi
NXP Employee
NXP Employee

The PLL override is not recommended and also is not supported by default. 

Adrian

0 Kudos

318 Views
yipingwang
NXP TechSupport
NXP TechSupport

Hello Christian Reedy,


You could use QCVS tool to assist you to generate RCW file.


On T4240RDB, DDRCLK is 133.33MHz, if configure RCW[MEM_PLL_RAT](10-15) as 7:1, the DDR Data Rate is 1.867 GT/s, this configuration is used in T4240RDB JTAG configuration file provided in CodeWarrior.


On your custom board, DDRCLK is 100 MHz, if configure RCW[MEM_PLL_RAT](10-15) as 7:1, the DDR Data Rate is 1.4 GT/s.

If your problem remains, you could create a bareboard project with SRAM launch configuration enabled, then use it to connect to the target board to flash RCW to NOR flash, this could avoid using DDR to run flash algorithm. Please check whether DDR clock is as the expect result, please detect your hardware if necessary.


Have a great day,
TIC

-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------

0 Kudos