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Timing for UARTx_USR2[TXDC]?

Question asked by Kim Boendergaard on Aug 10, 2017
Latest reply on Aug 14, 2017 by Pavel Chubakov

According to the i.MX6 reference manuals UARTx_USR2[TXDC] goes high when TxFIFO and Shift Register is empty

My concern is that it is unclear whether parity (optional) and stop bit(s) are included in the term "Shift Register is empty"


If not I see no means to ensure all bits are transmitted before toggling UARTx_UCR2[CTS] while using it to control direction in RS485 mode.


Anyone who can confirm parity and stop bits are also covered by TXDC?

If not - are there other means to detect 'transmission fully complete'?


The lower a bit rate the higher risk of changing direction too soon and thus make an invalid 'last' character transmission


The reference manual deliberately say about UARTx_USR2[TXFE ] (in Transmitter FIFO empty Interrupt Suppression):


the interrupt flag is set when the last bit of the character has been transmitted, for example, before the transmission of the parity bit (if exists) and the stop bit(s).

But again - this is not TXDC