I am trying to configure PCIe RCs on t2080-based board. I have LaWs set up by u-boot as follows
target PCIe0 - 0xc:0x00000000, size 512M
target PCIe1 - 0xc:0x20000000, size 256M
target PCIe2 - 0xc:0x40000000, size 256M,
target PCIe3 - 0xc:0x60000000, size 256M
I leave LaWs as configured and inside OS I configure PCIe1 ATMUs as follows
PEXOTEAR2(PEX1) = 0xc20000000ULL >> 44 (aka 0)
PEXOTAR2(PEX1) = 0xc20000000ULL >> 12
PEXOWBAR2(PEX1) = PCI1_MEM_BUS (0xe0000000) >> 4
PEXOWAR2(PEX1) = 0x80000000 | 0x4 << 16 | 0x4 << 12 | 0x1c
PEXITAR1(PEX1) = 0x0
PEXIWBAR1(PEX1) = 0x0
PEXIWAR1(PEX1) = 0x80000000 | 0xf << 20 (target - DRAM) | 0x5 << 16 | 0x5 << 12 | 0x1F;
Then I assign bus address 0xe000000 to PCIe device`s BAR0, there are no any bridges between device and RC.
Then I map BAR0 into OS virtual space (0xe000000 bus address gets mapped to 0xc2000000ULL host physical address through outbound ATMU which in turn gets mapped into OS virtual address space)
Then I'm trying to access BAR0 from device driver (does not matter read or write) and immediately receive Machine Check exception. Looks like something was missed in the RC configuration, but I do not see what exactly, does anyone have an idea what may be wrong ?