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Inconsistency between AN4259 and P1020RM regarding GPIO8, GPIO9

Question asked by Andy Jones on Aug 7, 2017
Latest reply on Aug 9, 2017 by Serguei Podiatchev

I'm trying to avoid a GPIO inadvertently driving out when it should be configured as an input, and wanting to check the significance of a statement in AN4259:


AN4259 rev 1, 05/2014 section 20, GPIO Interface Pin Recommendations, states that

"When the eSDHC controller is not used, SDHC_CD and SDHC_WP are GPIOs configured as output."

Initial thoughts are that this statement appears to be at odds with P1020RM, rev 6, 01/2013, where, as might be expected, the initialised state following Reset is input, for all GPIO's.


However, I wonder whether another interpretation is that if the SDHC controller has been used and then is not used, then those GPIO lines are left as outputs.  This speculation seems unlikely, as SDHC uses these as inputs.


In either case, I've not yet identified what control turns the SDHC on (used) or off (unused), unlike for the SPI, where the ESPI_SPMODE register has an Enable eSPI bit.  I mention the SPI enable, because SPI clearly ties up some SDHC resources, and SPI clearly has an Enable.


Any clarification appreciated,




Andy Jones