LS1012A interface with two DDR3L of 1Gx* Layout routing

[nilavchoksi]

Hi,

I am working on Layout of LS1012A based custom board design and using two DDR3L for an interface.

I am using Fly-by method to route DDR3L so please help here to confirm the maximum length support for two DDR3L routing.

Routing details are as per below:

- Total differential Clock length: 2562 mils

- Processor to first DDR: 1420 mils

- first DDR to second DDR: 588 mils

- second DDR to termination: 461 mils

Address:

- Processor to first DDR3L maximum distance is 1500 mils (tolerance +/- 250 mil) 

- Total maximum distance(From processor to the second DDR3L) for Address Group is 2500 inch (tolerance +/- 250 mils within group) 

- Maximum distance between the second DDR3L to termination resistors is 600 mil(tolerance +/- 250 mils)   

Data:

Lower data byte group and Upper data byte groups are within 1-inch total maximum distance

Thank you in advance

[r8070z]

Have a great day,

There is application note AN3940 “Hardware and Layout Design Considerations for DDR3 SDRAM Memory Interfaces” on the NXP site. The NXP recommends it for the LA1012A too. I do not see that you violate the maximum length support for DDR3L routing. Tolerance for address traces looks big for me. Often address/command are matched to the clock signals within ±25 ps or approximately ±125 mil to each discrete memory component. As example of the LS1012A to DDR routing see application note AN11950 “DDR Interfacing for LS1012A” on the NXP site.

-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------

[nilavchoksi]

Hi,

Thank you for the answer and following same application note for DDR3L routing.