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LS1012A interface with two DDR3L of 1Gx* Layout routing

Question asked by Nilav Choksi on Aug 3, 2017
Latest reply on Aug 7, 2017 by Nilav Choksi



I am working on Layout of LS1012A based custom board design and using two DDR3L for an interface.

I am using Fly-by method to route DDR3L so please help here to confirm the maximum length support for two DDR3L routing.


Routing details are as per below:


- Total differential Clock length: 2562 mils

- Processor to first DDR: 1420 mils

- first DDR to second DDR: 588 mils

- second DDR to termination: 461 mils



- Processor to first DDR3L maximum distance is 1500 mils (tolerance +/- 250 mil) 

- Total maximum distance(From processor to the second DDR3L) for Address Group is 2500 inch (tolerance +/- 250 mils within group) 

- Maximum distance between the second DDR3L to termination resistors is 600 mil(tolerance +/- 250 mils)   



Lower data byte group and Upper data byte groups are within 1-inch total maximum distance


Thank you in advance