Hello,
We are using the AP5191 Application Note init.s and the S32 project startup.s files as a starting point to configure MPC5777c MMU and other setups. When we enable both Cores cache for the internal SRAM the system crashes. However if we only enable core-0 cache for the internal SRAM the system will continue the normal operation.
Our hardware and software setup is:
-We are using the MPC5777C EVBUG. Daughter board as a standalone (no mother board)
-Latest Lathuerback Trace32 software for debugging and loading code
-S32 Design Studio for Power Architecture, Version: 1.2, Build id: 170613
Anyone experience this issue? Any advice/guidance is well appreciated. I have attached the init.s fill from the AP5191. The line in question is the internal SRAM MMU configuration.
Under normal operation:
-On the daughter board....
--LED D5 – 5.0 V - ON
--LED D6 – 3.3 V - ON
--LED D7 – 1.25 V - ON
--The Orange LED that is next to the power is also ON
-The Lauterbach emulator can be connected to load and debug the code
-I can verify the software cycles
During failure operation (when the system crash):
-On the daughter board....
--LED D7 – 1.25 V – ON
--The Orange LED, LED D6 (5.0V), and LED 7 (1.25 V) are all OFF. Why enabling core-1 cache has anything to do with the power is very strange. Any explanation is well appreciated.
-The Lathuerback emulator CAN NOT connect to the processor (MPC5777C) to load or debug code. The debugger will state the system is in reset mode can’t be set to run (ready) mode.
I can provide an additional information if needed.
Thank you
***********************************08-24-2017***********************************
This issue is fixed from NXP Tech Support:
<<
I've attached two images, one showing what the user guides expects J513 to look like and the other showing how it changed on rev c.
On rev c J513 was basically split into two headers, J513 and J13. J13 Contains what was pins 7 & 8 of J513. So to get 1.25 V from the SBC, J13 should be shorted and J513 should have no jumpers on it.
All the other jumper settings in table 18 appear to be the same on rev C.
Let me know if this was the issue, if not I can dig further in.
Thank you for your interest in NXP Semiconductor products and
for the opportunity to serve you.
Best regards,
Peter
Technical Support
NXP Semiconductor >>
