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LPUART Rx using EDMA on LS1021A

Question asked by Murali Patta on Aug 1, 2017
Latest reply on Aug 6, 2017 by alexander.yakovlev

Hi,

I am trying to enable data transfer from LPUART FIFO buffers to a RAM buffer using EDMA. My ideal case is to achieve this with out interrupting the processor in the whole process. But with the current setup configuration (specified below) I am not able to trigger the DMA. I really appreciate if anyone could take a look at it and see if I am missing any pieces of the puzzle.

DMA MUX:
 
DMAMUX2_CHCFG2 - 0xA0 - Enable and source as LPUART RX1
EDMA Setup:
DMA_CR - 0x0000040C - Enable round robin group and channel arbitration
DMA_ERQ - First tried with 0x0004_0000 and then 0xFFFF_FFFF
TCD : - for 18 - Base address - 0x02C0_1240
 
Source Address - 0x0295_000C - LPUART RX 1 Data Register address
SOFF - 0x0 - Since we do not want to change source address after copy is done
ATTR - 0x0202 - 4bytes
NBYTES - 4
SLAST - 0
DADDR - RAM buffer address
DOFF - 4
CITER - 1
BITER - 1
DLASTSGA - 0
CSR - 0
 
LPUART Setup: Using LPUART1 RX
LPUART1_BAUD - 0x0F20_4036
LPUART1_CTRL - 0x002C_0000
LPUART1_FIFO -  0x0000_0088
LPUART1_WATER - 0x0001_0003
I am guessing that LPUART is not initiating/generating the DMA request when Rx Water level mark is reached.
Thanks,
Murali

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