Hi,
I am trying to enable data transfer from LPUART FIFO buffers to a RAM buffer using EDMA. My ideal case is to achieve this with out interrupting the processor in the whole process. But with the current setup configuration (specified below) I am not able to trigger the DMA. I really appreciate if anyone could take a look at it and see if I am missing any pieces of the puzzle.
Sorry for delayed response
I do not see anything incorrect in your register settings except LPUART1_FIFO
For the value "LPUART1_FIFO = 0x0000_0088" - if this is a read-back value, than this means FIFO size is only one dataword. In this case setting watermark to 1 is incorrect, LS1021A Reference Manual says:
Receive Watermark
When the number of datawords in the receive FIFO/buffer is greater than the value in this register field, an
interrupt or a DMA request is generated. For proper operation, the value in RXWATER must be set to be
less than the receive FIFO/buffer size as indicated by FIFO[RXFIFOSIZE] and FIFO[RXFE] and must be
greater than 0.
For further debugging please:
1. reconfigure DMAMUX2_CHCFG2 to always-on slot to check if everything is correct with DMA configuration.
2. verify that LPUART reception works and generates interrupt on watermark
Have a great day,
Alexander
TIC
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