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BT.1120 16 bit YUYV progressive mode.

Question asked by Robert Chapin on Aug 1, 2017
Latest reply on Aug 1, 2017 by igorpadykov

I am now working on an FPGA that sends BT.1120 16 bit YUYV progressive data through the CSI0 port in parallel mode.  I am having a hard time understanding what the imx6 expects for  the embedded codes, in particular the 4th byte. I have gathered from a combination of  the IMX6SDLRM spec and NXP support posts that embedded codes frame start, frame end, line start and line end are put on the upper data byte which is the Y data for this mode. The register CCIR_CODE_1 register talks on start of active line and end of active line so it is very confusing how many codes is actually needed. ( 2 or 4)

 

The 4 byte sequence is 0xff-00-00-xx  where xx is the code for the frame/line state.   There are no timing diagrams in your IMX6 spec for BT.1120 16 bit YUYV progressive for this mode and the ITU BT.1120 spec seems to only talk about 10 bit data for codes.

 

With the embedded codes that you  give me from answering the above question, what value do I program the CCIR_CODE_1 register. I have verified that CCIR_CODE_3 is programmed for 0xff0000 which I am sure is correct for the first three bytes of the embedded code.

 

I am pretty sure that I have been through all the posts on this also so it would be really great if you could give the answer with code values and what to program the CCIR_CODE_1 register for these code values.

 

 

Rob

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