AnsweredAssumed Answered

Timeout error while waiting for FLG bit in CPCR register to be cleared

Question asked by rvijay435 on Jul 31, 2017
Latest reply on Aug 2, 2017 by rvijay435

The issue is related to the timeout error while waiting for the Communications Processor to clear the FLG bit in CPCR register (CP Command Register).

The operation is when the FLG bit is set, we cannot give another command. Only when the CP clears the FLG bit set by Core, we can give other commands.

The SCCx (where x is from 1 to 4) for UARTs is configured as per section 21.21 in the MPC8280 Reference Manual. We are waiting on the CPCR FLG bit to be cleared for 6 SECONDS. But we still
see the timeout and the FLG bit is not cleared by Communications Processor.

Reference: MPC8280RM which can be found in http://www.nxp.com/docs/en/reference-manual/MPC8280RM.pdf.

Outcomes