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LPSPI Chip Select Frequency S32K144

Question asked by Vlad Damian on Jul 31, 2017

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Hello,

I am trying to understand some specs regarding SPI functionality on S32K144 processor.

First, I have opened and ran the LPSPI example provided. Then displayed my CHIP SELECT signal to the oscilloscope.

After configuring and checking all data transmited via SPI, I see that no matter what settings I do (related to the baudrate of transmission, BUS clock and other parameter changes), the CHIP select signal always waits between 20us-30us between two succesive transmissions. Other way said, The CHIP SELECT signal is HIGH, data is transmitted, then it goes LOW for aprox 20-30us, then the next data is transmitted.

This has anything to do with the SPI settings, or there are some interrupts used by Operating System (OSIF) to do something else between two consecutive transmissions?

I have attached some pictures (please check Δt value, at the bottom of graphic) .

Thank you!

Original Attachment has been moved to: lpspi_transfer_example.zip

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Daniel Martynek

Aug 1, 2017 6:14 AM

Hello Vlad,

The SDK example uses blocking functions that wait for a transfer to be completed. The next transfer is then delayed because a new message needs to be prepared. It should depend on Bus frequency.

Regards,

Daniel

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Vlad Damian Aug 1, 2017 7:56 AM

Hi Daniel,

Forgot to mention...

I have used the other method provided in the library. Also, I ran this transfer in DMA mode (for transferring with high speeds):

LPSPI_DRV_MasterTransfer(FSL_SEND, &masterDataSend, &masterDataReceive, BUFFER_SIZE);

So this function also uses some mechanisms for delays, in order to prepare for next message?

PS: I have tested the code provided in the cookbook also. This is working as specified (1us delay between two transfers). I am working to configure this example to run at highest speed, in DMA mode.

Thank you!

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Razvan-nicolae Tilimpea

@ Vlad Damian on Aug 1, 2017 10:39 PM

Hi Vlad,

Did you use the LPSPI example as it is?

If the answer is yes I think you observe that delay because each transfer is initiated after ADC conversion complete. If you want to evaluate only LPSPI driver I think you should remove ADC and PWM from this example and try to use higher buffer sizes.

The highest frequency tested with LPSPI module is 20MHz in DMA mode and the example code will be available on the next release (EAR 0.8.5).

Best regards,

Razvan

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Vlad Damian @ Razvan-nicolae Tilimpea on Aug 3, 2017 10:13 AM

Hi Razvan,

No, I didn't used the example as it was.

1.) The measurement was done after I commented the code related to the ADC and PWM and left just the the LPSPI_DRV_MasterTransfer function inside the infinite loop.

2.) I have used the LPSPI_DRV_MasterTransfer function, which is without blocking.

3.) I have tested various BUFFER_SIZEs.

What else should I try? Maybe I miss something obvious.

Thank you !

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Razvan-nicolae Tilimpea

@ Vlad Damian on Aug 3, 2017 10:37 AM

Hi,

Please share your project on this thread.

In you project did you use LPSPI_DRV_MasterSetDelay function? This function can configure the parameters like delay between transfers.

Other observation is that is not a good idea to use non-blocking transfers in infinite loop because almost all transfers returns STATUS_BUSY.

For basic tests I used blocking transfers in while loops with various buffers sizes and I didn't observed this issue.

Best regards,

Razvan

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Vlad Damian @ Razvan-nicolae Tilimpea on Aug 4, 2017 4:33 AM

Hi,

I have attached the project.

Is basically a demo code from examples with some minor modifications.

Thank you for help again !

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Razvan-nicolae Tilimpea

@ Vlad Damian on Aug 4, 2017 8:34 AM

Hi,

I checked your project and that delay is caused by the overhead for set-up and finish a transfer.

Also, if you configure the lpspi at 5Mhz the interrupt mode is not suitable for for handling this transfer. Please use DMA.

If you want to enable the DMA please check this post: eDMA & LPSPI .

Best regards,

Razvan

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Vlad Damian @ Razvan-nicolae Tilimpea on Aug 7, 2017 3:20 AM

Hi Razvan,

Ok. will check and return with some feedback.

Thank you for help !

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8 Replies

Daniel Martynek Aug 1, 2017 6:14 AM
Mark Correct
Correct Answer
Hello Vlad,
The SDK example uses blocking functions that wait for a transfer to be completed. The next transfer is then delayed because a new message needs to be prepared. It should depend on Bus frequency.

Regards,
Daniel
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Vlad Damian Aug 1, 2017 7:56 AM
Mark Correct
Correct Answer
Hi Daniel,
Forgot to mention...
I have used the other method provided in the library. Also, I ran this transfer in DMA mode (for transferring with high speeds):
LPSPI_DRV_MasterTransfer(FSL_SEND, &masterDataSend, &masterDataReceive, BUFFER_SIZE);

So this function also uses some mechanisms for delays, in order to prepare for next message?

PS: I have tested the code provided in the cookbook also. This is working as specified (1us delay between two transfers). I am working to configure this example to run at highest speed, in DMA mode.

Thank you!
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- Razvan-nicolae Tilimpea @ Vlad Damian on Aug 1, 2017 10:39 PM
  Mark Correct
  Correct Answer
  Hi Vlad,
  
  Did you use the LPSPI example as it is?
  If the answer is yes I think you observe that delay because each transfer is initiated after ADC conversion complete. If you want to evaluate only LPSPI driver I think you should remove ADC and PWM from this example and try to use higher buffer sizes.
  
  The highest frequency tested with LPSPI module is 20MHz in DMA mode and the example code will be available on the next release (EAR 0.8.5).
  
  Best regards,
  Razvan
  Like • Show 0 Likes0
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  - Vlad Damian @ Razvan-nicolae Tilimpea on Aug 3, 2017 10:13 AM
    Mark Correct
    Correct Answer
    Hi Razvan,
    No, I didn't used the example as it was.
    1.) The measurement was done after I commented the code related to the ADC and PWM and left just the the LPSPI_DRV_MasterTransfer function inside the infinite loop.
    2.) I have used the LPSPI_DRV_MasterTransfer function, which is without blocking.
    3.) I have tested various BUFFER_SIZEs.
    What else should I try? Maybe I miss something obvious.
    Thank you !
    Like • Show 0 Likes0
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    - Razvan-nicolae Tilimpea @ Vlad Damian on Aug 3, 2017 10:37 AM
      Mark Correct
      Correct Answer
      Hi,
      
      Please share your project on this thread.
      In you project did you use LPSPI_DRV_MasterSetDelay function? This function can configure the parameters like delay between transfers.
      Other observation is that is not a good idea to use non-blocking transfers in infinite loop because almost all transfers returns STATUS_BUSY.
      For basic tests I used blocking transfers in while loops with various buffers sizes and I didn't observed this issue.
      
      Best regards,
      Razvan
      Like • Show 0 Likes0
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      - Vlad Damian @ Razvan-nicolae Tilimpea on Aug 4, 2017 4:33 AM
        Mark Correct
        Correct Answer
        Hi,
        I have attached the project.
        Is basically a demo code from examples with some minor modifications.
        Thank you for help again !
        Like • Show 0 Likes0
        Actions
        Razvan-nicolae Tilimpea @ Vlad Damian on Aug 4, 2017 8:34 AM
        Mark Correct
        Correct Answer
        Hi,
        
        I checked your project and that delay is caused by the overhead for set-up and finish a transfer.
        Also, if you configure the lpspi at 5Mhz the interrupt mode is not suitable for for handling this transfer. Please use DMA.
        If you want to enable the DMA please check this post: eDMA & LPSPI .
        
        Best regards,
        Razvan
        Like • Show 0 Likes0
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        Vlad Damian @ Razvan-nicolae Tilimpea on Aug 7, 2017 3:20 AM
        Mark Correct
        Correct Answer
        Hi Razvan,
        Ok. will check and return with some feedback.
        Thank you for help !
        Like • Show 0 Likes0
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LPSPI Chip Select Frequency S32K144

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