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Recommended SPI-Prescaler Settings for TWR-MEM

Question asked by Scott Kerstein on Jul 27, 2017
Latest reply on Aug 3, 2017 by xiangjun.rong

Hello,

 

I'm using the TWR-K64 board, TWR-SER along with the TWR-MEM board in the Tower system.  What are the recommended SPI-prescaler settings to get the K64 to communicate with SPI Flash on the TWR-MEM board?

 

The TWR_MEM Jumpers for this chip are as follows: J-14(1-2) and J4(1-2).

 

Here are my software settings (Using KSDK 1.2.0):

 

    DSPI_HAL_SetDelay(m_pSpiBase[m_instance], (dspi_ctar_selection_t)configData.clkTransAtt, 0, 4, kDspiPcsToSck);

    DSPI_HAL_SetDelay(m_pSpiBase[m_instance], (dspi_ctar_selection_t)configData.clkTransAtt, 0, 4, kDspiLastSckToPcs);

    DSPI_HAL_SetDelay(m_pSpiBase[m_instance], (dspi_ctar_selection_t)configData.clkTransAtt, 0, 1, kDspiAfterTransfer);

    DSPI_HAL_SetContinuousSckCmd(m_pSpiBase[m_instance], SYS_FALSE);

 

configData.clkTransAtt  = SPI_CLK_TRANSFER_ATTRUBUTES configuration (below enumeration)

 

/*! @brief DSPI Clock and Transfer Attributes Register (CTAR) selection*/

typedef enum SPI_CLK_TRANSFER_ATTRUBUTES

{

    SPI_CLK_TRANSFER_ATTRUBUTES_MASTER_OR_SLAVE = 0,   /*!< CTAR0 selection option for master or slave mode */

    SPI_CLK_TRANSFER_ATTRUBUTES_MASTER,                /*!< CTAR1 selection option for master mode only */

    SPI_CLK_TRANSFER_ATTRUBUTES_EOL

} SpiClkTransferAttr_t;

 

 

Clock info from the Oscilloscope

kDspiPcsToSck = 614ns

kDspiLastSckToPcs = 614ns

Spec on this device is (min of 5ns)

Timing between clock cycles (rising edge to rising edge) is 2.074us

 

 

Spi Port Configurations are as follows:

 

PIN MUX

    #if(DEVELOPMENT_BOARD_TYPE==BLD_USING_TWRK64F120M_DEV_BOARD)

          BSP_PORT_PTD_PIN3, BSP_PORT_FUN_ALT_2 //SPI0_SIN  (MISO)

          BSP_PORT_PTD_PIN2, BSP_PORT_FUN_ALT_2 //SPI0_SOUT (MISO)

          BSP_PORT_PTD_PIN0, BSP_PORT_FUN_ALT_2 //SPI0_PCS0 (ChipSel)

          BSP_PORT_PTD_PIN1, BSP_PORT_FUN_ALT_2 //SPI0_SCLK (SpiClock)

    #endif

 

PORT/BUS: BSP_SPI_BUS_SPI_0

IRQ Priority: Normal

 

#if(DEVELOPMENT_BOARD_TYPE==BLD_USING_TWRK64F120M_DEV_BOARD)

{

    500000UL,                                     ///< U32 baudRate; in bps

   8,                                            ///< U8 bitsPerFrame; defines the frame size for the device transaction; range is 4 to 32

   false,                                        ///< BOOL contChipSelect; if set true, chip select always remains active (not useful)

    SPI_CLK_TRANSFER_ATTRUBUTES_MASTER_OR_SLAVE///< SPI_CLK_TRANSFER_ATTRUBUTES_t clkTransAtt; Master or Master/slave role (CTAR0, or CTAR1)

   SPI_PCS0,                                     ///< SPI_PERIPHERIAL_CHIPSELECT_t peripheralCS; selection for the device chip select pin

    SPI_PCS_ACTIVE_LOW,                           ///< SPI_PERIPHERAL_CHIPSELECT_POLARITY_t polarityCS; shift polarity for the chip select pin

    SPI_CLOCK_POLARITY_ACTIVE_HIGH,               ///< SPI_CLOCK_POLARITY_t clkPolarity; clock polarity for the shift (idle state of SCLK)

    SPI_CLOCK_PHASE_LATCH_ON_LEADING_EDGE,        ///< SPI_CLOCK_PHASE_t clkPhase; clock phase for the shift;

                                                              -SPI_CLOCK_PHASE_LATCH_ON_LEADING_EDGE = command data is latched on leading edge of the clock pulse

    SPI_MSB_TRANSFER_FIRST,                       ///< SPI_SHIFT_DIRECTION_t shiftDirection; MSB or LSB first

},

#endif

 

 

Thanks, in advance.

Scott

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