ARM or Power Architecture

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ARM or Power Architecture

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nenwensoh
Contributor I

Hi, I will like to know the road map for power architecture processors for the next decade or so as we are deciding to go with either the ARM or Power architecture processor. Are there plans to stop designing new processors for the Power Architecture?

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4,408 Views
jfrey
Contributor IV

I am also very interested in this. As a consumer of the PPC chips development seems to have stagnated and ARM has been improving by leaps and bounds.

It looks like someone is picking up the reigns for RISC development as opensource.

RISC-V - Wikipedia 

The RISC-V authors aim to provide several CPU designs freely available under a BSD license. Such licenses allow derivative works, such as RISC-V chip designs, to be either open and free, like RISC-V itself, or closed and proprietary.

By contrast, commercial chip vendors such as ARM Holdings and MIPS Technologies charge substantial license fees for the use of their patents.[7] They also require non-disclosure agreements before releasing documents that describe their designs' advantages and instruction set. Many design advances are completely proprietary, never described even to customers. The secrecy prevents public educational use, security auditing, and the development of public, low–cost free and open-source software compilers, and operating systems.

However there's one design decision that has me scratching my head. It may make it a non-starter for future automotive use.

The embedded subset[edit]

An instruction set for the smallest "embedded" CPUs (set "E") is reduced in other ways: Only 16 of the 32-bit integer registers are supported. Floating-point instructions should not be supported (the specification forbids it as uneconomical), so a floating-point software library must be used.[3] The compressed set "C" is recommended. The privileged instruction set supports only machine mode, user mode and memory schemes that use base-and-bound address relocation.[14]

Correspondents have proposed even smaller, nonstandard, 16-bit "RV16E" ISAs: One would use a 16x16-bit integer register file, using the standard "EIMC" ISAs (including 32-bit instructions.) Another proposal would only use the 16-bit "C" instructions with an 8x16-bit register file. A full RV16EG was said to be possible with a completely recoded ISA.[36]

IBM still does PPC development but seems to have been concentrating on their server products.

POWER8 - Wikipedia 

Power Architecture - Wikipedia 

At the same time it looks like ARM has been catching up and has the Cortex-R line of processors is now ISO26262 certified.

ARM Takes Critical Step for Functional Safety | EE Times

In a crucial step to help IC vendors design SoCs compliant to functional safety standards such as ISO 26262 in the automotive industry, ARM released Thursday (Jan. 22) a comprehensive safety document package for its Cortex-R5 processor.

https://www.electronicsweekly.com/market-sectors/embedded-systems/arm-polishes-cortex-r5-iso26262-sa... 

The ARM Compiler is now TÜV SÜD certified, allowing for safety-related software development up to ISO 26262 ASIL D and IEC 61508 SIL 3 without further tool chain qualification activities.

Cortex-R5 – ARM Developer 

Improved reliability and high error resistance safety features for safety critical applications including bus Error Checking and Correction (ECC).

Ability to detect both systematic and random faults in the core.

Support for dual-core lock-step and split-lock configurations and advanced system level features to achieve twice the performance.

Simplified certification effort with the optional Safety Documentation Package for standards such as ISO 26262 and IEC 61508, and enable higher levels of certification to be obtained.

I would be very interested in some Coretex-R5 vs MPC57xx benchmarks. Given the longevity of how long most of "our" products last in market 

And NXP employees, I know, I know, you can't talk about it. It's still proprietary and confidential. That doesn't mean those of us that have the privilege/misfortune [depending on who you talk to] of using this architecture won't speculate on the future of it.

4,408 Views
EAlepins
Contributor V

‌Jed F wrote:

I would be very interested in some Coretex-R5 vs MPC57xx benchmarks. Given the longevity of how long most of "our" products last in market

We've compared a single core of the MPC5777C (e200z7 @ 264MHz) with the Texas Instruments TMS570LC4357 (Cortex-R5 @ 300 MHz), both at maximum performance (but code running from Flash) and we've got that MPC5777C is ~15% more performant than TMS570LC.:smileyhappy:

4,408 Views
jfrey
Contributor IV

Thanks. Do you have any publishable results? One thing I hate about our industries is everyone is so hush hush thinking that a simple benchmark will ruin their competitive advantage.

Was that floating or fixed point? Any flash file size differences?

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4,408 Views
EAlepins
Contributor V

No, benchmark is made with proprietary source code. I can however say the source code is generated from models (model-based) and the code is very linear (not that much loops). It is a control application (in, logic, out). It has 300 000 lines of code (without comments or blank lines). The benchmark accesses no true I/O or drivers (they are stubbed with SW).

Uses 32bits floating-point. Comparison was done with VLE for PowerPC and with Thumb-2 for ARM. Code size is 19% smaller for the TMS570LC: ARM wins there! PowerPC compiler used is CodeWarrior 10.5 for MPC5xxx (Freescale/Metrowerks, not GCC). ARM compiler is IAR.

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andrei_skok
NXP Employee
NXP Employee

Please contact your local NXP sales office or any of NXP Distributor for ARM and PowerPC roadmaps.

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