we have made a custom board base on C290PCIe_RDB Rev B version, the same DDR3 chip, the same CPLD hardware type. even we programmed the same cpld file using oamp-v2.2 version.
after power on , we got the asleep and ready waveform as attched picture showed. it is very strage the asleep signal seem ok, but ready signal is strage.
Is the power on sequence issue or wrong por config issue? need your urgent help, thank!!!!
by the way the IFC_CLK0 signal is normal 50MHZ as the RDB board tested.