C293 custom board ready signal stay low issue

[depengshan]

we have made a custom board base on C290PCIe_RDB Rev B version, the same DDR3 chip, the same CPLD hardware type. even we programmed the same cpld file using oamp-v2.2 version.

after power on , we got the asleep and ready waveform as attched picture showed. it is very strage the asleep signal seem ok, but ready signal is strage.

Is the power on sequence issue or wrong por config issue? need your urgent help, thank!!!!

by the way the IFC_CLK0 signal is normal 50MHZ as the RDB board tested.

[alexander_yakov]

Both READY and ASLEEP negated means the core is in power-saving mode (doze or nap).

In other words, the core is not "full on", but in halted mode. After reset, the core may be held in "halt" mode if, for example, boot sequencer is used.

Have a great day,
Alexander
TIC

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[depengshan]

hi, Alexander:

   thanks for your reply!!!

   It seem the C293 core always in "halt" mode since power on. The boot sequencer now set to default, which means the boot sequencer is disabled. No I2C ROM is accessed.

    how can we set the C293 core in "full on" mode?

    I check all the power supply, all the Power-on reset sequence, all the POR configuration, they are all correct, exactly the same POR configuration with the C293Pcie-RDB. Why the RDB borad ready singal can assert while our new board ready singal is negation?

[alexander_yakov]

The core may be in "halt" mode if "cfg_cpu_boot" is sampled low at reset. Please look C29x Reference Manual, Section 4.5.4.15 for details.

[depengshan]

hi, Alexander:

   We have checked all the POR configuration, all the power supply. "cfg_cpu_boot" is sampled high at reset , please see the attchment picture. 

   Which factor would affect C293 in halted mode if POR configuration is correct? thanks!!!

[alexander_yakov]

1. You said "we have made a custom board base on C290PCIe_RDB Rev B version" - please specify the exact (full list) of differences between your board and C290PCIe_RDB.

2. You said "We have checked all the POR configuration" - please submit me POR values you are using.

[depengshan]

1. please see the attchment schmatic, the biggest difference is some pin, for example, page11 IRQ pin left unconnected, not pull up as AN4660SKMM mentioned.

2. please see the attchment por_config.rar. 

thanks!!!

[alexander_yakov]

According to your schematic, configuration pin cfg_ddr_speed[1] is not pulled down - resistor R541 is "NC"

However, according to por_config scope screenshots, configuration pin cfg_ddr_speed[1] is driven "low" at reset.

According to C29x Reference Manual, Table 4-25, this "low" value is incorrect for given combination of DDR clock ratio and cfg_ddr_speed[0] settings.