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Information on the L2 Cache Controller for the I.MX6 ULL?

Question asked by Robert Stewart on Jul 26, 2017
Latest reply on Jan 12, 2018 by Yuri Muhin


I'm doing bare metal coding on an SOC containing an I.MX6 ULL. I've going through the NXP Applications Processor Reference Manual for this processor and can find no details on the L2 cache controller, like its mmio address or the controller name. Is it a PL310 controller similar to an A9 processor?


Thanks for any insight you can give me.