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i.MX6SX L2 cache issue

Question asked by Abraham Díaz on Jul 26, 2017

Hi, All,

 

We have designed our own PCB using i.MX6SX SABRE SDB board as a reference. The CPU model of this development board is MCIMX6X4EVM10AB and we are using the model MCIMX6X1EVO10AB in our custom PCB. The problem is that we are not able to enable the L2 cache in our custom PCB.

 

When the kernel starts and configures / enables the L2 cache (L2C-310 r3p2), the CPU hangs. If we delete the L2 cache definition from DTB, the kernel does not configure / enable the L2 cache and the system starts normally (although the performance is really poor because the cache is disabled). However, we are able to enable the L2 cache in the u-boot as we have already checked reading the 0x00a02100 register and it seems to work properly.

 

We have the following specific hardware and software configurations:

 

Hardware

  • Model: i.MX6SX MCIMX6X1EVO10AB (MCIMX6X4EVM10AB in i.MX6SX SABRE SDB) . According to NXP documentation, our model does not include the following modules:
    • 2D&3D GPU
    • PCIe
    • LVDS
    • Video ADC
  • DDR: Nanya 2x NT5CB64M16GP-DII with size of 256 MBytes (MICRON 2x MT41K256M16HA-125 with a size of 1 GByte in i.MX6SX SABRE SDB)). The layout is almost the same for both boards.
  • PMIC: MC32PF3000A3EP (MMPF0200F6AEP in i.MX6SX SABRE SDB). We have done all required modifications which are explanined in AN5161 application note ("Powering an i.MX 6SX-based System using the PF3000 PMIC").

 

Software

  • U-boot: 2015.04 version. We have tried with the latest version (2017.07), and the issue is also present. We have done the following changes in the u-boot configuration compared to i.MX6SX SABRE SDB:
    • In include/configs/mx6sxsabresd.h file:
      • We have modified the RAM size from SZ_1G to SZ_256M.
      • We have disabled the PCIe.
    • In board/freescale/mx6sxsabresd/mx6sxsabresd.c file, we have modified the pin configuration.
    • Device Configuration Data (DCD). We have run the "DDR Stress Test Tool" and updated calibration registers in DCD. Additionally, we have also modified some registers in DCD according to I.MX6SX_DDR3_Script_Aid_V0.01.xlsx. imximage.cfg file attached to this post.
  • Kernel version: 4.4.7 with rt16 real time patch. Kernel configuration attached to this post.
  • DTS: The default kernel DTS for i.MX6SX SABRE SDB with little modifications.

 

It is important to point out that we had used successfully the same kernel and u-boot versions in the i.MX6SX SABRE SDB development board.


Thanks for reading and any help will be highly appreciated!

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