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DDR3L - T1024 Issue

Question asked by Ram Krishnan on Jul 24, 2017
Latest reply on Aug 11, 2017 by Ram Krishnan

We have a board based on the T1024RDB design. The problem that we see is that some udimm modules work on these boards while others do not. The ones that do work need to have different MEM_PLL_RAT setup from the T1024RDB. We have to set it to 0xa to get it to work.


But there is a setting in which multiple modules work. The T1024RDB has the MEM_PLL_RAT set to 16 while the setting on our baord seems to be to set the rcw MEM_PLL_RAT to 7(8 also seems to work but there are some 1 bit EDAC errors which do get corrected) and in the uboot code to fake out the MEM_PLL_RAT to be 16 i.e the DDR Controller registers (from FE008000) are set based on a speed of 1600MTs.


I looked for erratas for the T1024 but could not see any that mentions MEM_PLL_RAT fix where in the RCW could set the DDR PLL to send out the wrong clock.


Any help in figuring out this issue would be very much appreciated. Random trial and error of different combinations seems to take a long time.


Thank you,

Ram Krishnan