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How to make Imx6q's memory controller to entry power down mode? 

Question asked by shuai wang on Jul 24, 2017
Latest reply on Aug 2, 2017 by igorpadykov

 As described in imx6q reference manual, automatic active/precharge power down entry to a specific chip select can be
activated by configuring the ESDPDC register:

       • PWDT_0/PWDT_1 - define the number of idle cycles before entering power down, can be different value per chip select.
      • SLOW_PD - In case of DDR3 memory is configured to use slow precharge power down then this bit should be set as well.
      • BOTH_CS_PS - The MMDC can either set each chip select independently to power down, according to its idle state, or set both chip selects to power downonly if both in idle state for the configured period.
      • Few paramters must be configured in addition:
      • Timing parameters at ESDCFG0[tXP and tXPDLL].
      • ODT timing at ESDOTC[tAOFPD, tAONPD, tANPD and tAXPD]

 

I have set these register when initializing the MMDC,but the imx6q con't automatic entry power mode. Is there anyone could give me some suggestions?  thank you.

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