I am designing custom board using LS1012A processor and interface with two 1Gx8 DDR3L micron DDR3L chip.
During layout, I am facing issue of routing of data lines so that as per AN3940 (Hardware and Layout Design
Considerations for DDR3 SDRAM Memory Interfaces) I have swapped the datalines in D0 to D7 at first DDR3L end.
Also, attached swapped connections of first DDR3L with Processor.
So, will it work for me? because I can't see any information or guide to change this bits from firmware configuration level and confusion on the connections.
Looking for your help.