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Variscite var_som_mx6 ksz9031 PHY issue

Question asked by Ameer Hamza on Jul 21, 2017
Latest reply on Jul 25, 2017 by Ameer Hamza

Dear all,



I am working on Ethernet development for Variscite var-som-mx6, without using any boot-loader or linux (using custom OS). Doing all the Ethernet driver development from the scratch. The default state of PHY for var-som-mx6 board is set to Power Down mode (LEDs are off at start-up even is Cable is plugged). The particular PHY shares RD0/MODE0, RD1/MODE1, RD2/MODE2, RD3/MODE3, RXCLK/PHYAD2 and RX_DV/CLK125_EN pins (e.g. RDx/MODEx Same pin can either be configure as RDx or MODEx).
Since PHY was currently in POWER DOWN mode, so we configure MODEx/RDx pins to GPIO level HIGH as mentioned in strapping option for RGMII mode. Then we enable clock for PHY by configuring RX_DV/CLK125_EN to GPIO High. Then we hard reset the PHY by GPIO1_25 pin after delaying for 10 millisecond. After resetting PHY gets alive and Lights are lid up. But when we reconfigure MODEx pins to RDx pins PHY becomes dead. After every reconfiguration of RDx pins PHY leds lost its brightness a little and after configuring all the pins to RDx pins, PHY gets totally dead. And we can not Read or Write from the PHY, but if we do not reconfigure pins from MODEx to RDx we can read or write the PHY device.
So my question is that why KSZ9031 PHY gets dead if we reconfigure from Strapping Configuration (MODE0/MODE1/MODE2 high, RGMIi mode) pins to RDx pins ?

I also have u-boot source available and I am using same sequence mentioned in setup_iomux_enet() {from line number 431-449, link uboot-imx/mx6var_som.c at imx_v2015.04_4.1.15_1.1.0_ga_var01 · varigit/uboot-imx · GitHub}, but some how not able to figure out what I am doing wrong.

Any help would be very highly appreciated.