Change IMX6UL BSP From 512MB(256x16) to 256M(128x16)

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Change IMX6UL BSP From 512MB(256x16) to 256M(128x16)

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nachodiz
Contributor III

Dear all,

Our First Custom I.MX6UL PCB was using Micron 512 MB (As the EVK Board), also updating calibration Results Board Was Working Very Fine

Now, our Second PCB version haves Alliance Memory AS4C128M16D3L-12BIN 256MB to reduce costs, but after inserting the same SD card that we was using with first pcb version it hangs Loading Kernel ...

We are updating again the DDR confics at uboot but we see that original BSP is created only for 512MB

What aditional changes do we need to perform to tell linux and uboot that we only have 256MB?

Something like this perhaps? (1u * 256 * 1024 * 1024) ???

tere.png

NOTE WE HAVE 128X16 (256MB)

U-Boot 2016.03 (May 18 2017 - 23:33:32 +0300)

CPU:   Freescale i.MX6UL rev1.1 528 MHz (running at 396 MHz)
CPU:   Industrial temperature grade (-40C to 105C) at 47C
Reset cause: POR
Board: MX6UL 14x14 EVK
I2C:   ready
DRAM:  512 MiB
MMC:   FSL_SDHC: 0, FSL_SDHC: 1
*** Warning - bad CRC, using default environment

Display: TFT43AB (480x272)
Video: 480x272x24
In:    serial
Out:   serial
Err:   serial
switch to partitions #0, OK
mmc0 is current device
Net:   FEC1
Error: FEC1 address not set.

Normal Boot
Hit any key to stop autoboot:  0
switch to partitions #0, OK
mmc0 is current device
switch to partitions #0, OK
mmc0 is current device
reading boot.scr
* Unable to read file boot.scr *
reading zImage
5293984 bytes read in 247 ms (20.4 MiB/s)
Booting from mmc ...
reading imx6ul-14x14-evk.dtb
37198 bytes read in 29 ms (1.2 MiB/s)
Kernel image @ 0x80800000 [ 0x000000 - 0x50c7a0 ]
## Flattened Device Tree blob at 83000000
   Booting using the fdt blob at 0x83000000
   Using Device Tree in place at 83000000, end 8300c14d
Modify /soc/aips-bus@02000000/bee@02044000:status disabled
ft_system_setup for mx6

Starting kernel ...

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Yuri
NXP Employee
NXP Employee

Hello,

 

  In Uboot file “include/configs/mx6ullevk.h” check / modify (if needed) parameters :

 - CONFIG_NR_DRAM_BANKS: Number of ddr banks.

 - PHYS_SDRAM_SIZE: Configure the DDR size in MB.

 - PHYS_SDRAM: Physical address for the DDR memory.

 

   In U-boot file “board/freescale/mx6ullevk/imximage.cfg”, the Device Configuration Data (DCD)

table should be modified at least regarding numbers of DRAM columns and

rows, assuming the timings are the same as for previous DRAM part.

Use MMDC Core Control Register (MMDC_MDCTL) at 21B_0000 for it.

  The line similar to “DATA 4 0x021B0000 0x84180000” in the DCD table is responsible

for MMDC_MDCTL settings. ROW and COL bit fields should be set according to DRAM Datasheet values.

Regards,

Yuri.

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gusarambula
NXP TechSupport
NXP TechSupport

Hello Nacho Diz,

I would recommend using the attached i.MX6UL DDR3 DRAM Register Programming Aid to set up the required registers for the new size of the DRAM. Please read the following information before using this tool:

This is the detailed programming aid for the registers associated with DRAM initialization (DDR3) of the MX6UL. The last work sheet tab in the tool formats the register settings for use with the ARM DS5/RealView debugger. It can be manually converted by the user to a DCD file format used by uboot or other bootloaders (note the removal of debugger specific commands in this tab). The programming aids were developed for internal Freescale validation and development boards.

 

This tool serves as an aid to assist with programming the DDR interface of the MX6UL and is based on the DDR initialization scripts developed by the R&D team and no guarantees are made by this tool.

 

The following are some general notes regarding this tool:

  • Refer to the "How To Use" tab in the tool as a starting point to use this tool.
  • Note that in the "DStream .ds file" tab there are DS5 debugger specific commands that should be commented out or removed when using the DRAM initialization for non-debugger specific applications (like when porting to bootloaders).
  • This tool may be updated on an as-needed basis for bug fixes or future improvements.  There is no schedule for aforementioned maintenance.
  • The write leveling calibration values in the programming aid are initialized to 0x0.  As the MX6UL supports only a x16 data bus interface and most customers may opt to use a single chip x16 DDR3 device, the need for write leveling is diminished.  In fact, even if the customer opts to use two x8 DDR3 devices, they would, ideally place these devices close enough to one another to not require write leveling. 

 

 I hope this helps!

Regards,

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