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Variation in number of cycles for Load/Store in different memory regions?

Question asked by HIMANSHU DOSHI on Jul 19, 2017
Latest reply on Jul 28, 2017 by HIMANSHU DOSHI

Hello to all,

I am considering Load and Store instructions for different memory regions and wanna analyzed their respective effect in the energy-consumption. From my script:


"STR.W R6,[R0]\t\n" 

"STR.W R6,[R0]\t\n"




"STR.W R6,[R0]\t\n" (1000times as interrupt)


and on the basis of the value of R0 register, the number of cycles are varying. For an example: 

SRAMX Memory Location: LDR R0,=#40000002 ;  => Number of cycles:  8

SRAM0 Memory Location: LDR R0,=#20000002 ;  => Number of cycles:  2 

SRAM1 Memory Location: LDR R0,=#20010002 ;  => Number of cycles:  2

SRAM2 Memory Location: LDR R0,=#20020002 ;  => Number of cycles:  2Memory Map LPC54114


This is what the result I am getting. And if in the case of accessing the instructions with offset, will show a huge change in the number of cycles up to 12 cycles each instruction


Along with that, while trying to access the Flash memory there is no detection of the interrupt


Can any body explains me such behavior??. Also, kindly find the attached memory map.


My target board is LPC 54114 and my target processor is ARM Cortex-M4.


Thanking you,



Himanshu Doshi