Thank you for your reply. According to the documentation you pointed out, iMX6ULL DDR controller is able to run at an intermediary frequency (100MHz).
By shortcutting busfreq driver, we manage to force to iMX6ULL to reach this mode. However, in order to make a proper modification of this driver, we would like to know how is the automatic mechanism that makes the frequency switch between low / audio / high. It seems to be very linked to counter variables :
high_bus_freq_mode = 1;
med_bus_freq_mode = 0;
low_bus_freq_mode = 0;
audio_bus_freq_mode = 0;
Is there a documentation where the general process is explained? If not, could you summarize the idea here?
Thank you for your help,