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i.MX8 platform - pin delays / rules for DDR interface

Question asked by Martin Tatak on Jul 18, 2017
Latest reply on Jul 20, 2017 by Diego Adrian Cuevas

Hello, I have two questions regarding to the i.MX8 platform: 

 

1) Pin delays for the iMX8 package 
We have the reference Allegro board file LAY-29336_A.brd and there are some info inside the constraint manager. 
Could somebody explain these numbers in Relative Delay - Delta: Tolerance? Attached is a picture with details.

 

There are two questions for this picture: 
A) Why there are not used pin delays in this board file? Could somebody convert the blue numbers to pin delays?
B) Why the red numbers are not with the same length?
 
  

2)  Could somebody tell us minimal length for the LPDDR4 lines? 

 
Thank you & best regards,
 

Martin Tatak 

 

Team Leader PCB Layout 

Phone: +420 511 151 413 

Email: Martin.Tatak@congatec.com 

congatec s.r.o. | Sochorova 3232/34 | 616 00 Brno | Czech Republic

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