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MPC5777M: How to ensure shared memory coherency

Question asked by alain felici on Jul 17, 2017
Latest reply on Jul 18, 2017 by Peter Vlna

Hello all, 


We are writing an application requiring shared memory berween core and cache enabled (for perfomance issue). 

The memory will be updated by two ways: The classical one (store memory) and DMA. 



I don't know how to ensure cache coherency in these cases. Is someone can help us?


Thanks for you help.