Hi I am using P1012 ESPI in master mode and have few queries regarding it . Can someone please answer these ?
1.The eSPI Event Register (SPIE) reports events . I do not wan't interrupts , so I have set SPIM to 0 to mask the interrupts. The manual says that we should clear SPIE by writing a 1. Now suppose I have set
eSPI Mode Register (SPMODE) to 0x80001D03 which enables interrupts , and sets RXTHR -3 , TXTHR -29. I wan't to do a 4 byte write and a 4 byte read , hence the values of RXTHR and TXTHR. For writing I use the following code -
*******************************************************
For writing
*********************************************************
spieData = SPI_REG_READ_32 (SPIE);
/*check if TNF is 1 i.e TX fifo is not full , and TXT is set i.e Transmit FIFO has at most
* TXTHR -1 (29-1) - 28 bytes. So we can do a 4 byte write.
*/
while( (spieData & (0x100) == 0) || (spieData & (0x800)) == 0 ){
/*SPI core not ready , wait */
if(timeout >= sendSpansionFlashTransTimeout){
printf("%s :Error !! TNF/TXT not set spieData = 0x%08x\n",__FUNCTION__,spieData);
return ERROR;
}
timeout = timeout+1;
sysUsDelay (100);
}
/*can write the data now */
SPI_REG_WRITE_32 (SPITF, *(VUINT32 *) cmd);
*****************************************************
For reading
*****************************************************
spieData = SPI_REG_READ_32 (SPIE);
timeout =0;
/*check if RNE(22nd bit) is 1 i.e RX fifo is not empty , and RXT(18th bit) is set i.e Receive FIFO has at least
* RXTHR +1 (3+1) = 4 bytes. So we can do a 4 byte read.
*/
while( (spieData & (0x200) == 0) || (spieData & (0x2000)) == 0 ){
/*SPI core not ready , wait */
if(timeout >= readIdReceiveTimeout){
printf("%s Error !! RNE/RXT not set spieData = 0x%08x in empty buffer\n",__FUNCTION__,spieData);
return ERROR;
}
timeout = timeout+1;
sysUsDelay (100);
}
/* read the SPIRF in 32 bit, to empty the buffer */
readData = SPI_REG_READ_32 (SPIRF);
Is this implementation correct ? Is there a better way to read /write ?
2. Suppose (SPMODE) is 0x80001D0 and SPIM to 0x0. I have more than 4 bytes in my RX FIFO so I assume that the RXT (bit 18) of SPIE will be set. Now I read few bytes and the number of bytes become less than 4 bytes , say 2 bytes then will the RXT(bit 18) clear automatically or I have to clear it every time it is set to 1 , so see any further changes. Is this behaviour same for every bit of SPIE i.e I have to clear every time it sets to 1 ?(As mentioned RNE,TNF,RXCNT and TXCNT are not affected by clear SPIE).
3. Suppose I have to read 65000 bytes from a flash with 24 bit address and one byte instruction.. So I set the SPCOM to 0x0004FDEB . Now the rx buffer is only 32 bytes but here the CPU will send 65000+4 = 65004 clock cycles so the CPU rx buffer will overflow . Am I correct ? If yes then what is the recommended way to read large amount of data from a flash , say 16mb, which will involve multiple SPCOM writes.
4. What happens when the EN (bit 0) of the SPMODE is toggled from 0 to 1 OR 1 to 0. Which all registers are impacted ? What happens if the frame is not transmitted fully ?
Thanks in advance.
Thanks for the reply . Sorry If some of my questions were not clear.
1.Yes , you are correct I should read SPIE in the while loop. I missed it.
2.The SPMODE is set to 0x80001D03(it was a typo) and SPIM to 0x0. My question is regarding the SPIE register.
Suppose the TXE bit is set in the ESPI. I read that bit and did a write , now I wan't to read again the TXE bit to
determine when the TX FIFO becomes empty. Can I read the TXE bit again , without clearing it the first time or do I have to clear it every time I read it, so that I can get proper status next time I read the TXE bit. Does similar logic clear /read logic applies to DON,RXT , RXF and TXT bit as well ?
3. Will read less then 32 bytes to avoid overflow.
4. Suppose I have written 0x00000004 to SPCOM(so number of characters in the frame is 5). Now , suppose after sending 2 characters I stopped(due to some error). Now I wan't to start the complete transaction again. So again
I write 0x00000004 to SPCOM and this time I sent 5 characters , but in this case I do not see the DON bit in SPIE being set to 1 . Even if I do soft reset of CPU and try the transaction again I still see DON bit in the SPIE is not set to 1. Why is this ? How to handle such broken writes/reads ?
5. Is there a way to reset the CPU espi block ?
Thanks,
Ankit
Have a great day,
> Which all registers are impacted ?
This question is fuzzy. You should care for SPMODE itself. Any bits in SPMODE must not change when EN is set.
>What happens if the frame is not transmitted fully ?
The frame will not be transmitted fully.
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