AnsweredAssumed Answered

Problem of Communication between M4 and A9 on SOLOX

Question asked by Alessandro Maggi on Jul 13, 2017
Latest reply on Jul 13, 2017 by igorpadykov

We need to transfer some data from M4 to A9. For this purpose we use a shared memory in RAM (DDR). M4 writes the data and then rise a GPIO to tell the A9 data is available. M4 is running free RTOS with cache disabled. A9 is running linux 4.1.5 with PREEMT RT patch , cache enabled and it is suspended on the GPIO change with the poll primitive. Usually the process works, but sometimes when the A9 reads old data. We suspect that it's accessing its own cache and not the RAM. We tried to disable the cache in the kernel but without success (kernel hangs very early after u-boot launch it we don't see a single print).


So questions are:

  1.  Is there a way to declare a part of the RAM as uncacheable in the A9 core when running Linux ?
  2. Are there better alternatives for communication between cores ? We need to be very fast (-> we need to minimize latency).