What is the acquision period of the SAR ADC in the LPC1500

[iainrist1]

I am interested in using the LPC1500 in a new design and need to know some ADC parameters not stated in the datasheet.

What is the acquision period of the SAR ADC in the LPC1500?

From that I can calculate analogue bandwidth and conversion period.

[soledad]

Hi,

The ADC controller uses the system clock as a bus clock. The system clock or the asynchronous ADC clock can be used to create the ADC clock which drives the successive approximation process:

• In the synchronous operating mode, this ADC clock is derived from the system clock. In this mode, a programmable divider is included to scale the system clock to the maximum ADC clock rate of 50 MHz (72 MHz in 10-bit mode).
• In the asynchronous mode, an independent clock source is used as the ADC clock source without any further divider in the ADC. The maximum ADC clock rate is 50 MHz (72 MHz in 10-bit mode) as well. In this mode, the ADC clock frequency must not exceed ten times the system clock.

A fully accurate conversion requires 25 ADC clocks.

I hope this helps,

Have a great day,
Soledad

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