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i.MX6 DDR3 write leveling for T topology

Question asked by Toshishisa Sugiyama on Jul 11, 2017
Latest reply on Oct 11, 2017 by Toshishisa Sugiyama

Hi, 

 

I read below thread.

https://community.nxp.com/message/810441?commentID=810441#comment-810441 

Then I don't think Write leveling calibration need for T topology. However, it should set something right value in  MMDC_MPWLDECTRLx. SABRESD board use fixed value 0x001F001F.  

How does this value chose? 

Can this value 1F use as standard for custom board?

 

Best Regards,

Sugiyama

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