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74HCT74PW - On power up, What is the default STATE of pin Q

Question asked by jeevaaraamsethuraman on Jul 9, 2017
Latest reply on Jul 20, 2017 by Tomas Vaverka

Part #: 74HCT74PW
Function: D-type ?ip-?op
Description: Dual D-type ?ip-?op with set and reset; positive-edge trigger;  TTL-enabled

 

Query:
On power up, what is the STATE of pin Q (When CP = 0)?


My expected output will be HIGH, only when the SD=HIGH, RD=HIGH and also CP is in positive rising edge. But, I’m getting output pin-5 (1Q) as HIGH, when the CP is in low state.

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