We encountered some question in DDR3.We have produced about 1 thousand boards,and we got several (5~6) board fail to boot from EMMC,after checked the DDR3,we found ddr3 caused the booting failing.
our DDR3 device is :
I used the ddr stress test tool v2.6 to test one of our faulted custom board，I got some strange results in HW write leveling process.
The DQS group's write leveling delay results is the same :31/256 CK delay. the nomarl board 's results is below:
Write leveling calibration completed, update the following registers in your initialization script
MMDC_MPWLDECTRL0 ch0 (0x021b080c) = 0x004E004E
MMDC_MPWLDECTRL1 ch0 (0x021b0810) = 0x0041004A
MMDC_MPWLDECTRL0 ch1 (0x021b480c) = 0x002B0029
MMDC_MPWLDECTRL1 ch1 (0x021b4810) = 0x002D0041
Write DQS delay result:
Write DQS0 delay: 78/256 CK
Write DQS1 delay: 78/256 CK
Write DQS2 delay: 74/256 CK
Write DQS3 delay: 65/256 CK
Write DQS4 delay: 41/256 CK
Write DQS5 delay: 43/256 CK
Write DQS6 delay: 65/256 CK
Write DQS7 delay: 45/256 CK
I read the manual " 188.8.131.52 Hardware Write Leveling Calibration"
every DQS write leveling should repeat step 5~7 and adds 1/8 cycle delay between DQS and clk every times,then fine tuning must be executed to find precise delay value ,the resolution of the tuning is 1/256 clk.
What clues can we get through this result?
does the 31/256 results mean that write leveling only execute the first 5~7 step then the ddr device sampled the CLK and got the transition from 0 to 1,then tuining the result to 31cycles?