AnsweredAssumed Answered

Flexcan problem on KE1xF

Question asked by Giovanni Gherardi on Jul 8, 2017
Latest reply on Nov 30, 2017 by Giovanni Gherardi

HI, I'm developing an application with a KE16F256. I generated the sdk with pins and clock and inside I found examples for the TWR-KE18F evaluation board. I tried to use the loopback, loopback transfer and interrupt examples but without any success. I'm not able to send / receive. If I use the blocking tx the tx function hangs. The only thing that seems working is that when I set the loopback on, everytime I call the non blocking transfer I have my callback called to notify the TX idle.

I configured correctly Tx and Rx pin alternate function. I enabled the clock for the flexcan.

I'm quite new to kinetis world (I'm coming from STM32). 

Is there a check list to see if I'm not fogotting something?

 

Just for reference I attach some code:

 

this is the can init function:

 

void flexcan_configure(uint32_t baudRate)
{

/* Init FlexCAN module. */
flexcan_config_t flexcanConfig;
flexcan_rx_mb_config_t mbConfig;
/*
* flexcanConfig.clkSrc = kFLEXCAN_ClkSrcOsc;
* flexcanConfig.baudRate = 125000U;
* flexcanConfig.maxMbNum = 16;
* flexcanConfig.enableLoopBack = false;
* flexcanConfig.enableSelfWakeup = false;
* flexcanConfig.enableIndividMask = false;
* flexcanConfig.enableDoze = false;
*/
FLEXCAN_GetDefaultConfig(&flexcanConfig);
#if (!defined(FSL_FEATURE_FLEXCAN_SUPPORT_ENGINE_CLK_SEL_REMOVE)) || !FSL_FEATURE_FLEXCAN_SUPPORT_ENGINE_CLK_SEL_REMOVE
flexcanConfig.clkSrc = kFLEXCAN_ClkSrcPeri;
#endif /* FSL_FEATURE_FLEXCAN_SUPPORT_ENGINE_CLK_SEL_REMOVE */
flexcanConfig.enableLoopBack = true;
flexcanConfig.baudRate = baudRate;

FLEXCAN_Init(CAN_IF, &flexcanConfig, CAN_CLK_FREQ);

/* Create FlexCAN handle structure and set call back function. */
FLEXCAN_TransferCreateHandle(CAN_IF, &flexcanHandle, flexcan_callback, NULL);

/* Enable Rx Message Buffer interrupt. */
FLEXCAN_EnableMbInterrupts(CAN_IF, 1 << RX_MESSAGE_BUFFER_NUM);  // CAN_IF = CAN0
EnableIRQ(CAN_IRQn);     


/* Setup Rx Message Buffer. */
mbConfig.format = kFLEXCAN_FrameFormatStandard;
mbConfig.type = kFLEXCAN_FrameTypeData;
mbConfig.id = FLEXCAN_ID_STD(0x680);
FLEXCAN_SetRxMbConfig(CAN_IF, RX_MESSAGE_BUFFER_NUM, &mbConfig, true);

/* Setup Tx Message Buffer. */
FLEXCAN_SetTxMbConfig(CAN_IF, TX_MESSAGE_BUFFER_NUM, true);

// /* Enable Rx Message Buffer interrupt. */
// FLEXCAN_EnableMbInterrupts(CAN_IF, 1 << RX_MESSAGE_BUFFER_NUM);
// EnableIRQ(CAN_IRQn);

}

 

 this is my send function:

 

 

void flexcan_send(uint16_t ID, uint8_t data[8],uint8_t DLC)
{
/* Prepare Tx Frame for sending. */
txFrame.format = kFLEXCAN_FrameFormatStandard;
txFrame.type = kFLEXCAN_FrameTypeData;
txFrame.id = FLEXCAN_ID_STD(ID);
txFrame.length = DLC;
txFrame.dataWord0 = CAN_WORD0_DATA_BYTE_0(data[0]) | CAN_WORD0_DATA_BYTE_1(data[1]) | CAN_WORD0_DATA_BYTE_2(data[2]) |
CAN_WORD0_DATA_BYTE_3(data[3]);
txFrame.dataWord1 = CAN_WORD1_DATA_BYTE_4(data[4]) | CAN_WORD1_DATA_BYTE_5(data[5]) | CAN_WORD1_DATA_BYTE_6(data[6]) |
CAN_WORD1_DATA_BYTE_7(data[7]);

txXfer.frame = &txFrame;
txXfer.mbIdx = TX_MESSAGE_BUFFER_NUM;
FLEXCAN_TransferSendNonBlocking(CAN_IF, &flexcanHandle, &txXfer);


/* Send data through Tx Message Buffer using polling function. */
// FLEXCAN_TransferSendBlocking(CAN_IF, TX_MESSAGE_BUFFER_NUM, &txFrame);
}

 

this is my board init:

 

 

void BOARD_InitPins(void) {
CLOCK_EnableClock(kCLOCK_PortA); /* Clock Control: 0x01u */
CLOCK_EnableClock(kCLOCK_PortB); /* Clock Control: 0x01u */
CLOCK_EnableClock(kCLOCK_PortC); /* Clock Control: 0x01u */
CLOCK_EnableClock(kCLOCK_PortD); /* Clock Control: 0x01u */
CLOCK_EnableClock(kCLOCK_PortE); /* Clock Control: 0x01u */

CLOCK_EnableClock(kCLOCK_Flexcan0); /* Clock Control: 0x01u */


PORT_SetPinMux(PORTA, PIN1_IDX, kPORT_PinDisabledOrAnalog); /* PORTA1 (pin 49) is configured as ADC0_SE1 */
PORT_SetPinMux(PORTA, PIN10_IDX, kPORT_MuxAlt7); /* PORTA10 (pin 58) is configured as JTAG_TDO */
PORT_SetPinMux(PORTA, PIN3_IDX, kPORT_MuxAlt6); /* PORTA3 (pin 47) is configured as LPUART0_TX */
PORT_SetPinMux(PORTA, PIN4_IDX, kPORT_MuxAlt7); /* PORTA4 (pin 64) is configured as JTAG_TMS */
PORT_SetPinMux(PORTA, PIN5_IDX, kPORT_MuxAlt6); /* PORTA5 (pin 63) is configured as JTAG_TRST_b */
PORT_SetPinMux(PORTA, PIN6_IDX, kPORT_PinDisabledOrAnalog); /* PORTA6 (pin 38) is configured as ACMP1_IN0 */
PORT_SetPinMux(PORTA, PIN7_IDX, kPORT_PinDisabledOrAnalog); /* PORTA7 (pin 37) is configured as ADC0_SE3 */
PORT_SetPinMux(PORTB, PIN0_IDX, kPORT_MuxAlt2); /* PORTB0 (pin 34) is configured as LPUART0_RX */
PORT_SetPinMux(PORTB, PIN2_IDX, kPORT_MuxAlt3); /* PORTB2 (pin 32) is configured as LPSPI0_SCK */
PORT_SetPinMux(PORTB, PIN3_IDX, kPORT_MuxAlt2); /* PORTB3 (pin 31) is configured as FTM1_CH1 */
PORT_SetPinMux(PORTB, PIN5_IDX, kPORT_MuxAlt3); /* PORTB5 (pin 18) is configured as LPSPI0_PCS1 */
PORT_SetPinMux(PORTB, PIN6_IDX, kPORT_PinDisabledOrAnalog); /* PORTB6 (pin 12) is configured as XTAL */
PORT_SetPinMux(PORTB, PIN7_IDX, kPORT_PinDisabledOrAnalog); /* PORTB7 (pin 11) is configured as EXTAL */
PORT_SetPinMux(PORTC, PIN14_IDX, kPORT_MuxAsGpio); /* PORTC14 (pin 30) is configured as PTC14 */
PORT_SetPinMux(PORTC, PIN15_IDX, kPORT_MuxAsGpio); /* PORTC15 (pin 29) is configured as PTC15 */
PORT_SetPinMux(PORTC, PIN16_IDX, kPORT_MuxAsGpio); /* PORTC16 (pin 28) is configured as PTC16 */
PORT_SetPinMux(PORTC, PIN2_IDX, kPORT_MuxAlt3); /* PORTC2 (pin 21) is configured as CAN0_RX */
PORT_SetPinMux(PORTC, PIN3_IDX, kPORT_MuxAlt3); /* PORTC3 (pin 20) is configured as CAN0_TX */
PORT_SetPinMux(PORTC, PIN4_IDX, kPORT_MuxAlt7); /* PORTC4 (pin 62) is configured as JTAG_TCLK */
PORT_SetPinMux(PORTC, PIN5_IDX, kPORT_MuxAlt7); /* PORTC5 (pin 61) is configured as JTAG_TDI */
PORT_SetPinMux(PORTC, PIN6_IDX, kPORT_MuxAlt2); /* PORTC6 (pin 52) is configured as LPUART1_RX */
PORT_SetPinMux(PORTC, PIN7_IDX, kPORT_MuxAlt2); /* PORTC7 (pin 51) is configured as LPUART1_TX */
PORT_SetPinMux(PORTC, PIN8_IDX, kPORT_MuxAsGpio); /* PORTC8 (pin 36) is configured as PTC8 */
PORT_SetPinMux(PORTC, PIN9_IDX, kPORT_MuxAsGpio); /* PORTC9 (pin 35) is configured as PTC9 */
PORT_SetPinMux(PORTD, PIN1_IDX, kPORT_MuxAlt4); /* PORTD1 (pin 1) is configured as FTM2_CH1 */
PORT_SetPinMux(PORTD, PIN16_IDX, kPORT_PinDisabledOrAnalog); /* PORTD16 (pin 14) is configured as ACMP2_IN0 */
PORT_SetPinMux(PORTE, PIN1_IDX, kPORT_MuxAlt2); /* PORTE1 (pin 59) is configured as LPSPI0_SIN */
PORT_SetPinMux(PORTE, PIN11_IDX, kPORT_MuxAlt2); /* PORTE11 (pin 3) is configured as PWT_IN1 */
PORT_SetPinMux(PORTE, PIN2_IDX, kPORT_MuxAlt2); /* PORTE2 (pin 54) is configured as LPSPI0_SOUT */
PORT_SetPinMux(PORTE, PIN4_IDX, kPORT_MuxAsGpio); /* PORTE4 (pin 6) is configured as PTE4 */
PORT_SetPinMux(PORTE, PIN5_IDX, kPORT_MuxAsGpio); /* PORTE5 (pin 5) is configured as PTE5 */
PORT_SetPinMux(PORTE, PIN6_IDX, kPORT_MuxAsGpio); /* PORTE6 (pin 53) is configured as PTE6 */
PORT_SetPinMux(PORTE, PIN7_IDX, kPORT_MuxAsGpio); /* PORTE7 (pin 39) is configured as PTE7 */
}

/*******************************************************************************
* EOF
******************************************************************************/

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