10G Cortina Phy Debugging For Custom Design.

[vidyasagartata]

We are debugging 10G cortina 4317 phy for our custom T2080 design, able to phy id in the uboot, below is the uboot log for reference.

Since we are using new cortina phy in our design please let us know how to load the microcode and modification required sorce code.

Log:

---------------------------

EEPROM: Invalid ID (aa 55 aa 55)
PCIe1: disabled
PCIe2: disabled
PCIe3: disabled

PCIe4: Root Complex, no link, regs @ 0xfe270000
PCIe4: Bus 00 - 00
In:    serial
Out:   serial
Err:   serial
Net:   bus in board file = 0x7FAEDD60
bus in board file = 0x7FAEDD60
Fman1: Uploading microcode version 106.4.18
bus # 0x7FAEEF70
phy id = 0x70000
After operation phy id = 0x704D2
bus # 0x7FAEEF70
phy id = 0x70000
After operation phy id = 0x704D2
bus # 0x7FAEEF70
phy id = 0x70000
After operation phy id = 0x704D2
bus # 0x7FAEEF70
phy id = 0x70000
After operation phy id = 0x704D2
bus # 0x7FAEF030
CORTINA_PHY_ADDR1 0x10
CORTINA_PHY_ADDR2 0x11
bus = 2142171184
 addr = 0x10
phy id = 0x23E50000
After operation phy id = 0x23E52002
PHY reset timed out
bus # 0x7FAEF030
CORTINA_PHY_ADDR2 0x11
bus = 2142171184
 addr = 0x11
phy id = 0x23E50000
After operation phy id = 0x23E52002
PHY reset timed out
FM1@DTSEC1, FM1@DTSEC2, FM1@DTSEC3 [PRIME], FM1@DTSEC4, FM1@TGEC1, FM1@TGEC2
Hit any key to stop autoboot:  0
=>
=> mdio list
FSL_MDIO0:
4 - Generic PHY <--> FM1@DTSEC3
5 - Generic PHY <--> FM1@DTSEC4
8 - Generic PHY <--> FM1@DTSEC1
9 - Generic PHY <--> FM1@DTSEC2
FM_TGEC_MDIO:
16 - Generic 10G PHY <--> FM1@TGEC1
17 - Generic 10G PHY <--> FM1@TGEC2
=>

Thanks,

Vidya

[ufedor]

The PHY is not an NXP product. Please ask the device manufacturer to provide the microcode.

For the microcode deployment please refer to the NXP Linux SDK Infocenter (T2080RDB):

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