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Additional clock gates (LPCG) for i.MX7 ENET clocks

Question asked by Vincent Siles on Jul 4, 2017
Latest reply on Jul 7, 2017 by Vincent Siles

Hi !

Following my question about i.MX7 ENET clock gate in i.MX7 clock tre: ENET_REF_CLK_ROOT gates , I am now interested in the LPCG part of the tree. Some clocks, like ENET_AXI_CLK_ROOT or ENET1_TIME_CLK_ROOT have an associated LPCG, and some like ENET1_REF_CLK_ROOT don't have one.

 

From the clock tree, we can see that:

  1. ENET_AXI_CLK_ROOT has a LPCG but it is not documented
  2. ENET1_TIME_CLK_ROOT is using LPCG CCGR112 and ENET2_TIME_CLK_ROOT is using LPCG CCGR113
  3. ENET1_REF_CLK_ROOT and ENET2_REF_CLK_ROOT don't have any LPCG

 

However in NPX Linux bsp (linux-imx.git - i.MX Linux Kernel ) we can see the following code

clks[IMX7D_ENET1_REF_ROOT_CLK] = imx_clk_gate4("enet1_ref_root_clk", "enet1_ref_post_div", base + 0x44e0, 0);
clks[IMX7D_ENET1_TIME_ROOT_CLK] = imx_clk_gate4("enet1_time_root_clk", "enet1_time_post_div", base + 0x44f0, 0);
clks[IMX7D_ENET2_REF_ROOT_CLK] = imx_clk_gate4("enet2_ref_root_clk", "enet2_ref_post_div", base + 0x4500, 0);
clks[IMX7D_ENET2_TIME_ROOT_CLK] = imx_clk_gate4("enet2_time_root_clk", "enet2_time_post_div", base + 0x4510, 0);

 

It refers to LPCG CCGR78, 79, 80 and 81.

 

There are two issues here: the "REF" clocks shouldn't have any LPCG, and the "TIME" clocks are using the wrong LPCG.

There is an unfinished discussion on the arm-kernel mailing list (see RE: i.MX7 clock support broken — ARM, OMAP, Xscale Linux Kernel ) where it seems that it is a mistake, but the guy here never gave the feedback from the IC team.

 

Can anyone have a final answer to these clocks ? Is the RefMan accurate or is the linux driver correct ?

 

Best,

V.

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