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Question asked by Shubhangi Ghosh on Jul 4, 2017

I've been working on P1015 processor with e500 core, in standalone mode(without OS), using "Multi"GreenHills Compiler, the processor being connected to the host computer(with compiler) through GreenHills Probe. I have written some code to halt the processor core:

int counter =0;

asm("lis r12, 0x0080");

asm("mtspr hid0, r12"); //Enabling HID0[DOZE] bit - 40th bit in HID0




   asm("mfmsr r12");

   asm("oris r12,r12,0x0004"); //Enabling MSR[WE] bit-- to initialise power management


   asm("mtmsr r12"); //Enabling MSR[WE]


   ++counter; //checking if core halted, if counter not incremented

But the counter still keeps getting incremented, and the loop runs in an infinite loop. Is it because JTAG debugging provides some interrupt causing the processor to come out of halt state? If so, is there any way to check the halt status by checking some register bit? Or could it be because, the processor core is not connected to the power management unit? The E500CORERM datasheet says:

"The e500 does not implement its own doze, nap, and sleep modes. The core-halted and core-stopped states may correlate to the integrated device’s doze, nap, and sleep modes, but the e500 cannot be put into core-halted or core-stopped state without interaction with system integration logic. "

On setting HID0[DOZE] and MSR[WE], core halt signal is asserted. But what should exactly be done to ensure core is halted?