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i.MX 6 ULL Layout and Stack up

Question asked by Robert Billen on Jul 3, 2017
Latest reply on Jul 4, 2017 by Robert Billen

I am designing a new product with the i/MX 6 ULL at the heart. I have the NXP design guidelines. They use a fairly large PCB as the basis with 4 layers, medium sized through hole vias and all surface routing for the DDR3. I have seen some PCB's with the DDR butted right up against the processor and I am under pressure from my boss to emulate this design. However, my solution would be 8 layers for good plane shielding and possibly blind/buried uVias, however, my boss is also keen to keep costs low, like penny pinchingly low. (His suggestion is no blind/buried and 6 layers). Any advice?