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MIPI CSI2 frame synchronization with i.MX6Q

Question asked by Josh Watts on Jun 30, 2017
Latest reply on Jul 9, 2017 by Josh Watts

We are currently receiving progressive frames from a MachX02 via MIPI CSI2 on the i.MX6Q, but have so far been unable to solve one final issue. Similar to what is described in section 5 of the IPU TVIN app-note, our stream sometimes starts out-of-sync:

i.MX6Q MIPI CSI2 out-of-sync issue 

It is important to note that the stream "sticks" with this offset until we completely stop and restart the entire capture stream. It seems that the only time we get correctly synchronized frames is when the MIPI receiver begins receiving before our FPGA begin sending data. If our V4L2 sub-dev driver takes too long to return from ioctl_s_parm() then we end up with some amount of offset as above. Similarly, if something interrupts the stream, such as experimentally restarting the MIPI data stream from the FPGA without restarting the MIPI receiver, we end up with out-of-sync frames.

 

Our FPGA logic is producing frame-start/frame-end packets, but not line-start/line-end. When frames are not synchronized, we occasionally receive NFB4EOF errors but not on every frame. Most recently we tried to implement the patch provided in the TVIN app-note, even extending it to stop and restart our FPGA's output. Previously we also implemented frame-numbers in the frame-start packets. This appeared to improve the issue, 1 out of 10 starts fail down from 9 out of 10, but did not completely resolve the issue.

 

Does any one have any comments on why the IPU's FSU is not locking on to the next frame-start/vsync-edge?

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