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P2020 Local bus pll enable

Question asked by wang xiao on Jun 30, 2017
Latest reply on Jul 3, 2017 by wang xiao


I met the problem.Platform clock is 400MHz,i want to set local bus clock for 100MHz,so add in the .h file:

#define CONFIG_SYS_LBC_LCRR 0x00030002 /* local bus freq */

bit 0 PLL enable

clock divide 4


Clock ratio register (eLBC_LCRR)  bit 0 PBYP should be 0,means the PLL enable.

After set the register,  I read this register data is 0x80030002,bit 0 still 1 in bypass mode ,is that right?

(Additionally,Bypass mode ,local bus cycle time minnum 12ns,so the clock maxmum 83MHz)