Hi,
I met the problem.Platform clock is 400MHz,i want to set local bus clock for 100MHz,so add in the .h file:
#define CONFIG_SYS_LBC_LCRR 0x00030002 /* local bus freq */
bit 0 PLL enable
clock divide 4
Clock ratio register (eLBC_LCRR) bit 0 PBYP should be 0,means the PLL enable.
After set the register, I read this register data is 0x80030002,bit 0 still 1 in bypass mode ,is that right?
(Additionally,Bypass mode ,local bus cycle time minnum 12ns,so the clock maxmum 83MHz)
Solved! Go to Solution.
Thanks。
Progam:
clrsetbits_be32(&lbc->lcrr, LCRR_CLKDIV, CONFIG_SYS_LBC_LCRR);
__raw_readl(&lbc->lcrr);
isync();
the reason:
clrsetbits_be32(&lbc->lcrr, LCRR_CLKDIV, CONFIG_SYS_LBC_LCRR) mapping to
out_be32(&lbc->lcrr,inbe32(&lbc->lcrr) & (~LCRR_CLKDIV) | CONFIG_SYS_LBC_LCRR)
actually it does not change bit 0
solution:
*(volatile *)(&lbc->lcrr) = CONFIG_SYS_LBC_LCRR ;
then it‘s ok
Which processor is in question?
P2020
Please use debugger to debug U-Boot.
Thanks。
Progam:
clrsetbits_be32(&lbc->lcrr, LCRR_CLKDIV, CONFIG_SYS_LBC_LCRR);
__raw_readl(&lbc->lcrr);
isync();
the reason:
clrsetbits_be32(&lbc->lcrr, LCRR_CLKDIV, CONFIG_SYS_LBC_LCRR) mapping to
out_be32(&lbc->lcrr,inbe32(&lbc->lcrr) & (~LCRR_CLKDIV) | CONFIG_SYS_LBC_LCRR)
actually it does not change bit 0
solution:
*(volatile *)(&lbc->lcrr) = CONFIG_SYS_LBC_LCRR ;
then it‘s ok