Hi, @Mark Middleton
I read this thread, but I need more information.
I 'd like to know how waveform change when CK_FT0_DCC and CK_FT1_DCC register value were changed.
Could you look at attached SDCLK_CK_FTx_DCC_.xlsx file?
1. Which case is correct CASE1 (red frame) or CASE2(green frame) when CK_FTx_DCC value changed?
2. As the reference manual description, CK_FT0_DCC is the primary and CK_FT1_DCC is secondary and it is cascaded. Does it means if both register value set 001(51.5% high each), then clock duty would be 53% high cycle? if it doesn't work like this, how it work when both register set 001 and 100?