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CSI PIXCLK line being pulled low by the IPU during BT656 data transfer.

Question asked by Nathan Young on Jun 28, 2017
Latest reply on Jul 6, 2017 by Nathan Young

Hey, I'm trying to interface with a sensor using the BT656 protocol through the CSI. When the sensor is powered up but not attached to the IMX6, the clock sits nicely at 27MHz like it is supposed to. However, when the IMX6 is present, the pixel clock signal becomes sporadic, almost as if the CSI is pulling the clock low.
This also appears on reset.
When the IMX6 is power cycled, the clock returns to its nice 27MHz waveform, however part way into the start up procedure, the clock becomes corrupted again.
Is there a register somewhere that causes the CSI clock line to be pulled low at a particular frequency (to provide a clock to the sensor) or is there something more sinister going on here?

 

Thanks, Nathan

PS. I think I got a signal of 100MHz out of the clock line at some point. I figured this might be the frequency the CSI is pulling the clock line down at, but I'm not entirely certain.

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