CSI PIXCLK line being pulled low by the IPU during BT656 data transfer.

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CSI PIXCLK line being pulled low by the IPU during BT656 data transfer.

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nathanyoung
Contributor I

Hey, I'm trying to interface with a sensor using the BT656 protocol through the CSI. When the sensor is powered up but not attached to the IMX6, the clock sits nicely at 27MHz like it is supposed to. However, when the IMX6 is present, the pixel clock signal becomes sporadic, almost as if the CSI is pulling the clock low.
This also appears on reset.
When the IMX6 is power cycled, the clock returns to its nice 27MHz waveform, however part way into the start up procedure, the clock becomes corrupted again.
Is there a register somewhere that causes the CSI clock line to be pulled low at a particular frequency (to provide a clock to the sensor) or is there something more sinister going on here?

Thanks, Nathan

PS. I think I got a signal of 100MHz out of the clock line at some point. I figured this might be the frequency the CSI is pulling the clock line down at, but I'm not entirely certain.

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art
NXP Employee
NXP Employee

The most likely cause of the issue is that, by default in your software configuration, the CSI pixel clock pin is used for some purpose other than CSI pixel clock and is configured as some functional output in the IOMUX controller somewhere during the boot process. So, please check the IOMUX configuration first.


Have a great day,
Artur

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nathanyoung
Contributor I

Since this, I have spent some time modifying the IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16 pad control register values. I've used 0x1b0b0 and several other configurations to no effect.

The pixel clock is connected to a lower voltage clock source through an MAX3013 logic level translator, which requires a resistive load of greater than 25kOhm on the output line.

At this point I am unsure where to go from here.

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nathanyoung
Contributor I

Atrur, I have the pin configured in the device tree as follows.

MX6QDL_PAD_EIM_A16__IPU2_CSI1_PIXCLK 0x1

This corresponds to 0x0f4 (mux_reg) 0x408 (conf_reg) 0x8e0 (input_reg) 0x2 (mux_val) 0x1 (input_val) 0x1 (conf_val), which, as far as I can see, is correct.

These pins are then configured as a part of the driver code.  There still appears to be interference with the signal on the pad.

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