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What is the architectural difference between SPI2 on K65 and SPI2 on K64?

Question asked by Eric Texley on Jun 27, 2017
Latest reply on Jun 29, 2017 by Daniel Chen

I've enclosed two screen shots of the register set from the SPI2 peripheral taken while running on Freedom K64 (top) and a proprietary K65 design (bottom) using CodeWarrior 10.7.  Since the 1 word FIFO fix for SPI1, and SPI2 in MQX, MQX disables the FIFO function when it discovers a 1 word FIFO on SPI.  


On the K64, I see what I expect...TX, RX FIFO entries 2,3,4 are obviously disabled and not available.  But on the K65, they appear to mirror what is in the first FIFO entry.  Why?  Is it the peripheral that's different? or the underlying bus connections?  thanks again