What is the architectural difference between SPI2 on K65 and SPI2 on K64?

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What is the architectural difference between SPI2 on K65 and SPI2 on K64?

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erictexley
Contributor I

I've enclosed two screen shots of the register set from the SPI2 peripheral taken while running on Freedom K64 (top) and a proprietary K65 design (bottom) using CodeWarrior 10.7.  Since the 1 word FIFO fix for SPI1, and SPI2 in MQX 4.2.0.2, MQX disables the FIFO function when it discovers a 1 word FIFO on SPI.  

On the K64, I see what I expect...TX, RX FIFO entries 2,3,4 are obviously disabled and not available.  But on the K65, they appear to mirror what is in the first FIFO entry.  Why?  Is it the peripheral that's different? or the underlying bus connections?  thanks again

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danielchen
NXP TechSupport
NXP TechSupport

Hi Eric:

I would suggest you write to SPI, and then check the TX FIFO counter to see whether this FIFO is disabled.

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Regards

Daniel

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