I'm confused by the hardware triggering options for the ADC on the K22F. I need to sample two ADC channels at a rate governed by a PIT, and have both samples transferred by DMA to their buffers.
I'm not finding a clear description of the process in any one place. The ADC section is lacking, and the ADCxALTTRGEN bits are described in the SIM section, and the PDB section has more about the triggering, but putting it all together without a coherent description is making my head hurt.
If the PDB is required, my concern there is that (aside from not being sure how to configure this mode) I'm using the PDB to drive DAC conversions already. The DAC operates independently of the ADCs and will often be running at a different sample rate, and the sample rate may change during operation. Both the DAC interval value and the modulus value are set for the appropriate DAC sample rate, since the PDB docs say that the PDB timer also resets the DAC interval counter when it rolls over and I want to make sure that it's not causing DAC timing glitches. This makes me worry that using the PDB for ADC timing as well is going to cause problems.
It looks like I could access the channels I need through separate ADCs, but I'd prefer not to have both ADCs running DMA, since ADC1 is currently used for very infrequent sampling of things like internal temperature and battery voltage. ADC1 may also be run in fast bursts occasionally to generate entropy for crypto functions and I don't want to have to disrupt audio sampling for that.