We tried to measure the DRAM timing with 12GHz differential probe. It seems we have the similar problem on the measurement like the problem as below link. But in our schematic, the JTAG_MOD has been pulled down.
Our problem is that when we connect the DQS0 to the scope, the boot will hand up or can not boot, but connect the clock and DQ only without DQS connection can be ok to run the test. Once we connect the DQS, the boot will be fail. I have run the memtool and the stress test can be more than 620MHz, I think the timing tolerance should be enough. Do you have any idea for it?
I want to upload my schematic for you, can anyone see it here? I want to keep it confidential.