What's the correct way to control the sample rate on the I2S peripheral when using DMA transfers? I'm driving a TI DAC and have audio sources of various sample rates.
Until now, I've been feeding samples to the I2S data register in interrupt mode, with a PIT generating an interrupt every sample time and the I2S clock running at a few MHz. This works fine.
To reduce CPU utilization, I need to use DMA mode. Using Processor Expert, the only way I see to control the sample rate is to set the bit clock rate. Unfortunately the bit clock divider doesn't seem to have sufficient resolution to get the required accuracy across all source sample rates so I can't use that. (PE also doesn't support runtime configuration of the bit rate, but that's not a big deal.)
It seems like the way to do this ought to be to set the DMA channel up in periodic trigger mode with the PIT gating transfer requests, but PE won't do less than two words per transfer and says the hardware doesn't support a TX FIFO watermark of 1, and shows 2-8 to be the valid settings. That doesn't seem to match the reference manual - the manual just says the RFW field of I2Sx_RCR1 is a 3-bit field and says nothing about an offset, so I'd assume it takes 0-7.
Before I waste more time ripping out the PE I2S component to try it myself, can someone tell me how this is supposed to work?