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BSC9132 cfg_d1_ddr_pll_backup and cfg_d*_ddr_half_full_mode

Question asked by Jonathan Baird on Jun 23, 2017
Latest reply on Jun 27, 2017 by alexander.yakovlev



Our 9132 system, like the BSC9132QDS, has a signal 'cfg_d1_ddr_pll_backup', the state of which, I assume is readable in the DSP_DDR_PLL_BKUP bit of the GUTS_PORDSPDEVSR register after POR.

I don't understand the DSP_DDR_PLL_BKUP description in the 9132 Reference Manual. What does

'DSP_DDR PLL is working on Default Settings' and 'DSP_DDR PLL is working on Backup Settings' mean?

'cfg_d1_ddr_pll_backup' does not appear in the 9132 Reference Manual Rev 0 09/2014.

Is it possible that our setting 'cfg_d1_ddr_pll_backup' to '0' could explain why the state of the DDR2_HALF_FULL_MODE bit in the GUTS_PORDEVSR3 register is '1' when cfg_d2_ddr_half_full_mode is set to '0'?

All cfg_* signal states at POR seem to have their expected effects except for cfg_d1_ddr_half_full_mode and cfg_d2_ddr_half_full_mode. We are setting both of these to '0' which we thought would give us 'full frequency mode'. What we see is half frequency DDR operation.


Thank you in advance.


Jon Baird