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MPC560xB - Bad RAM initialization at startup

Question asked by Romain BENET on Jun 23, 2017
Latest reply on Jun 26, 2017 by Romain BENET

Hi,

 

I use CodeWarrior 10.6 with CPU MPC5604B (MPC560xB Qorriva) and I find an error on default source file when I create a project.

 

In the file MPC5604B_HWInit.c there is the function INIT_Derivative():

__asm void INIT_Derivative(void)
{
nofralloc
/* Disable WatchDog*/
// *(volatile unsigned int*)0xfff38010 = 0x0000c520;
e_lis r9,0x0001
e_add16i r9,r9,-15072
e_lis r8,0xfff4
e_stw r9,-32752(r8)

// *(volatile unsigned int*) 0xfff38010 = 0x0000d928;
e_lis r9,0x0001
e_add16i r9,r9,-9944
e_lis r8,0xfff4
e_stw r9,-32752(r8)
// *(volatile unsigned int*) 0xfff38000 = 0xff00000A;
e_lis r3,0xff00
se_addi r3,0x000a
e_lis r8,0xfff4
e_stw r3,-32768(r8)

/* SRAM initialization code*/
lis r11,L2SRAM_LOCATION@h
ori r11,r11,L2SRAM_LOCATION@l

/* Loops to cover L2SRAM, stmw allows 128 bytes (32 GPRS x 4 bytes) writes */
lis r12,L2SRAM_CNT@h
ori r12,r12,L2SRAM_CNT@l
mtctr r12

init_l2sram_loop:
stmw r0, 0(r11) /* Write 32 GPRs to SRAM*/
addi r11,r11,128 /* Inc the ram ptr; 32 GPRs * 4 bytes = 128B */
bdnz init_l2sram_loop /* Loop for 48k of SRAM */
blr
}

 

I set the important part of this function in bolt.

My problem is: the RAM is not initialized to value 0 by default.

Register r0 contains correctly value 0x00000000 (32 bits register) but there is other value write in all RAM memory.

But if I change the RAM access size from 128 to 4 bits the RAM is correctly initialized to value 0 as expected.

 

Where is the issue ? Bad initial source code or/and the ECU doesn't support 128 bits access ?

 

Thanks for your help.

Best regards,

Romain

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