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Questions about cache

Question asked by adrian onea on Jun 22, 2017
Latest reply on Jun 27, 2017 by Lukas Zadrapa

I am using S32R274 went through the reference manual and I have the following things I would like to clarify about the cache.

 

1. There is a cache invalidation mechanism which will force the next read to be from RAM. Is there a "flush". Is a flush required or will the hardware automatically update the SRAM independently?

 

2. The cash can be enabled/disabled for certain address ranges from both SMPU and the MMU. Why would you use one vs another one? I assume MMU is only relevant for the attached processor as one of the reasons.

 

3. Cash Invalidation.  Data Cash can be invalidated by writing a 1 in the DCINV from the L1CSR0 register or to L1FINV0. When would you use one vs another one? What is the differnce.

The manual does not explain what values go into CSET bits.

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