AnsweredAssumed Answered

[LS1043ARDB] Cores boot at different exception levels

Question asked by Zaid Albassam on Jun 20, 2017
Latest reply on Jun 26, 2017 by Zaid Albassam

Hi,

 

Iam having a problem with one of the LS1043ARDB board (Orange box), after U-boot loads my program, core0 is at exception level 2 (EL2), but the other cores boot at EL1 and get hang when trying to switch to EL2. I have another LS1043ARDB board (Gray box) and all the cores boot at EL2. the same uboot image is on both boards: "U-Boot 2016.012.0+ga9b437f (May 15 2016 - 11:01:10 +0800)", and both boards have the same dip switch settings. I have however noticed the below differences in the uboot boot log:

 

The orange box (not working):

CPLD:  V1.4

PPA Firmware: Version 0.1

EEPROM: NXID v1

 

The gray box (working):

CPLD:  V1.5

PPA Firmware: Version 0.2

EEPROM: Invalid ID (0b 0c 03 04)

 

 

Any idea why the orange box has the cores boot at different EL? Should  the color of the box mean something (like secure)?

 

Thanks,

Outcomes