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ADV7280M -> iMX6QDL

Question asked by Jason Gaiser on Jun 19, 2017
Latest reply on Jun 23, 2017 by Jason Gaiser



We're trying to use an ADV7280M to capture a NTSC/PAL CVBS signal and stream it over the network using a headless iMX6QDL.  We are using a fork of the 3.14-1.0.x-mx6 branch of the community kernel(  


I've searched the forums and went through countless posts and troubleshooting guides.  So far I've managed to get video capture somewhat working but only using Gated clock mode.  Using either mxc_v4l2_capture.out or a gstreamer-1.0 pipeline(using v0.11.1 of gstreamer1.0-plugins-imx), I can capture videos or still images but the colorspace and format is wrong(images are purple/pink).  I'm guessing the color issues could be fixed with colorspace conversion so for now I'm focusing on the sync issue.


It is not very easy for us to inspect the MIPI signals on our board, so I cannot guarantee that the BT.656 signals are present in the stream.  However, I am using the recommended initialization settings for the ADV7280M so I am confident they are present in the stream.  I have tried both 656 v3 and v4 but neither one works.  


My ioctl_g_ifparm() configuration which works is:


p->u.bt656.clock_curr = 27000000; // This should be zero, but we never get frames if it is.
p->u.bt656.nobt_vs_inv = 0; // -> Vsync_pol
p->u.bt656.nobt_hs_inv = 0; // -> Hsync_pol
p->u.bt656.latch_clk_inv = 0; // -> pixclk_pol
p->u.bt656.bt_sync_correct = 0; // -> ext_vsync: 0: No external VSYNC and HSYNC, embedded EAV and SAV will be used for SYNC.


I've tried varying all of the parameters.  I've tried using the I2P/deinterlacer on the ADV7280M with clock_curr set to both 0 or 1 and it does not make a difference.  I've also tried using the ADV7280M in both normal(i.e. capturing a CVBS camera signal) and free-run mode using various test patterns.  Unless clock_curr > 1(i.e. gated mode), I never receive frames("ERROR: v4l2 capture: mxc_v4l_dqueue timeout enc_counter 0").  


We are using one MIPI CSI-2 lane and virtual channel zero.  I've made the appropriate changes to the device tree and they are reflected in the register settings.


Can anyone suggest a solution?  I've double-checked our IPU and CSI register settings and they all look OK.  Data and clocks look OK, and data does seem to arrive in gated mode, so unless we have a data quality issue which is corrupting the bt.656 sync codes, I can't see anything wrong.  I double-checked the CCIR codes and they seem OK for BT.656 video:


CSI_CCIR_CODE_2 = 0x40596;
CSI_CCIR_CODE_3 = 0xFF0000;


assuming the bits, from MSB to LSB, indicate HVF values in the BT.656 sync codes.


I've heard from another engineer on the forums that they had success with a newer kernel(v4.1) so I am going to investigate back-porting any relevant changes in order to see if I can get things working.  Any suggestions are appreciated!