Question about GPC_MLPCR

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Question about GPC_MLPCR

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ko-hey
Senior Contributor II

Hi all 

I'm using i.MX7D and have question about GPC_MLPCR.

Q1
There are descriptions of MEMLP_RET_PGEN, MEM_EXT_CNT, MEMLP_ENT_CNT in the reference manual p.849 - p.850.
What is the reference clock for this Delay counter ?

Q2
There is a description of MEMLP_RET_SEL in the reference manual p.850.
What modes does "retention mode 2" and "retention mode 1" mean ?

Ko-hey

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Yuri
NXP Employee
NXP Employee

Hello,

  1.

   32 KHz clock is assumed.

2.

  MEMLP_RET_ SEL bit is not functional.

Have a great day,
Yuri

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Yuri
NXP Employee
NXP Employee

Hello,

  1.

   32 KHz clock is assumed.

2.

  MEMLP_RET_ SEL bit is not functional.

Have a great day,
Yuri

-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------

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ko-hey
Senior Contributor II

Hi Yuri

2.

i.MX7D don't care about whether MEMLP_RET_ SEL set "1” or not.

Am I correct ?

Is that a device specification ?

Ko-hey

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Yuri
NXP Employee
NXP Employee

Hello,

  yes, i.MX7D don't care about whether MEMLP_RET_ SEL set "1” or not.

Some options were planned but are not implemented. 

Regards,

Yuri.

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