Daniel Lundin

S08DZ clock problem when BDM isn't connected

Discussion created by Daniel Lundin on Aug 22, 2008
Latest reply on Aug 26, 2008 by Daniel Lundin
I'm having this really strange problem with a S08DZ16. When I run the program through the BDM, everything works fine. When the BDM is disconnected, the MCU resets itself during the clock setup code, which is as follows:


  MCGC1 = 0x80;                                  /* External reference clock */
        
  MCGC2 = MCGC2_RANGE_MASK |                     /* High frequencey range 1-16MHz */
          MCGC2_HGO_MASK   |                     /* High gain oscillator */
          MCGC2_LP_MASK    |                     /* Disable FLL / PLL in bypassed mode */
          MCGC2_EREFS_MASK |                     /* Oscillator requested */
          MCGC2_ERCLKEN_MASK;                    /* Enable the external reference clock */

  while((MCGSC & MCGSC_OSCINIT_MASK)==0)         /* Wait until the initialization cycle of the */
    ;                                            /* external crystal clock is completed        */

  while((MCGSC & 0x0C) != 0x08)                  /* While clock source is not external clock */
    ;

  MCGC3 = 0x00;                                  /* PLLS=0  -> FLL */




I set the clock the first thing I do after setting up the stack and the watchdog, so I get the crash rather instantly, after 500us. I can see that the reset line is then pulled low. I haven't managed to tell the proper reset cause from the SRS register, but it shows nothing.

I have the same hardware in another working DZ16 project, so I doubt it is related to hardware. The clock is a "Pierce" oscillator connection with 8MHz crystal, two 22pf caps and 1M ohm parallel with the crystal. Same design as I always use. If I check the oscillator with an oscilloscope, I see that I have a working clock on 8MHz running.

I tried clock setup code from the other working DZ16 project, and get the same error.

When the BDM is connected, everything works!

There is nothing on the reset line that could cause external resets. I have tried various values on the cap on the reset line, 100pF and 100n give the same problem. I have tried an external pull-up, in case the internal one wasn't working, same problem.

I checked the errata for the mask 3M05C. It mentions problems when you divide the clock by 1 and have the FLL enabled in bypassed mode. I have tried the workarounds in the errata and I get the same problem, so I doubt this is the cause. Various prescaler settings (divide by 1, 2, 4 etc) and enable/disable FLL in bypassed mode, all give the same problem.

The watchdog is set to 2^18 cycles, so it shouldn't be an issue.

I have the same issue on two boards, I'm pretty sure it isn't related to soldering.

Any ideas? Corrupt silicon batch?

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